About this calculator
This voltage divider bias PMOS common drain calculator analyzes a common-drain amplifier built with an enhancement-mode p-channel MOSFET and a voltage-divider bias network. Enter your component values and it immediately finds the DC operating point (ID, VSD and the operating region), the small-signal parameters, voltage, current and power gain, input and output impedance, the output waveform with its clipping limits, the frequency response and the power dissipated in every component. Each result can be expanded to show the equation used and the numbers substituted into it, so you can follow or check the working by hand.
How to use it
- Enter the supply rails (VDD and VSS; use 0 V for a grounded lower rail).
- Type the resistor values and pick Ω, kΩ or MΩ, or type suffixes directly, such as
4.7kor1M. Enterinffor an open-circuit load. - Set the MOSFET parameters: threshold voltage, device constant k, channel-length modulation λ and the square-law form your textbook uses.
- Enter the signal amplitude, frequency and source resistance Rsig.
- Switch on Frequency Response to add the coupling and internal capacitances and see the Bode plot, fL and fH.
- Use the link button to copy a URL that reopens the calculator with your values.
How the common drain amplifier works
In the common-drain (CD) amplifier, or source follower, the signal is applied to the gate and the output is taken from the source. The drain is at AC ground. The source follows the gate voltage offset by VGS, so the gain is a little below one and the output is in phase with the input.
The gate draws no current, so the input impedance equals the bias resistance, which is megohms in most designs. The output impedance is approximately 1/gm in parallel with RS. That is higher than an emitter follower’s because MOSFET gm is lower, typically tens to hundreds of ohms, but the source follower presents virtually no load to the stage driving it.
The voltage gain is gm·RL′/(1 + gm·RL′) with RL′ = RS ∥ RL ∥ ro, so it approaches one only when gm·RL′ is large. Source followers are used as input buffers for high-impedance sensors, as DC level shifters and as output stages.
Voltage-divider gate bias
A resistive divider sets the gate voltage: VG = VSS + (VDD − VSS)·R2/(R1 + R2). Because the gate draws no current, this voltage is exact. Unlike the BJT divider, there is no base current to load it, and the resistors can be made very large (megohms) to keep the input impedance R1 ∥ R2 high.
The source resistor RS provides negative feedback that stabilizes the drain current against threshold-voltage and k variations. With a source resistor the overdrive voltage satisfies VOV = (VDD − VG) − ID·RS − |VTP| together with ID = ½·k·VOV². The calculator solves this pair exactly and then checks whether the transistor is in saturation, triode or cutoff.
PMOS polarity and the square-law model
An enhancement-mode PMOS transistor conducts when the gate is more negative than the source by at least |VTP|; VTP itself is entered as a negative number. Current flows from source to drain, so the source connects toward the positive supply. The calculator reports VSG and VSD to keep the numbers positive, and the device is in saturation when VSD ≥ VSG − |VTP| = VOV. Holes have roughly two to three times lower mobility than electrons, so a PMOS needs a wider channel to reach the same kp as an NMOS. Once k is entered, the small-signal behavior is identical.
For the complementary circuit, see the Voltage Divider Bias NMOS Common Drain calculator. Comparing the two is a quick way to check your PMOS/NMOS sign conventions.
Equations used
The calculator follows the standard two-step method taught in electronics courses. It first solves the DC bias circuit with all capacitors open, then replaces the transistor with its small-signal model and the capacitors with short circuits to find the mid-band AC behavior. These are the equations for this common-drain circuit with the default component values.
DC analysis
- Gate Voltage (VG)
VG = VSS + (VDD − VSS) × R2 / (R1 + R2) (IG = 0) - Overdrive Voltage (VOV)
VSG = (VDD − VG) − ID·RS, ID = ½k·VOV² ⇒ VOV = [−1 + √(1 + 2k·RS·(VDD − VG − |VTP|))] / (k·RS) - Drain Current (ID)
ID = ½·k·VOV² (saturation assumed, λ neglected for bias) - VSD
VSD = (VDD − VSS) − ID·(RD + RS)
Small-signal analysis
- Transconductance (gm)
gm = k·VOV = 2·ID / VOV - Output Resistance (ro)
ro = 1 / (λ·ID) - Source AC Load (RL′)
RL′ = RS ∥ RL ∥ ro - Voltage Gain (Av = vo / vg)
Av = gm·RL′ / (1 + gm·RL′) - Overall Gain (Gv = vo / vs)
Gv = Av × Zin / (Zin + Rsig) - Current Gain (Ai = io / ii)
Ai = Av × Zin / RL - Power Gain (Ap)
Ap = |Av × Ai| - Input Impedance (Zin)
Zin = R1 ∥ R2 - Output Impedance (Zout)
Zout = RS ∥ ro ∥ (1/gm)
The frequency-response section adds one low-frequency pole for each coupling or bypass capacitor, using the resistance that capacitor sees (short-circuit time constants), and estimates the upper cut-off frequency from the transistor’s internal capacitances using open-circuit time constants. The exact −3 dB points are then found numerically from the combined response.
Worked example
The calculator opens with a ready-to-use example circuit: VDD = 12 V, VSS = 0 V, R1 = 1 MΩ, R2 = 1 MΩ, RD = 0 Ω, RS = 2 kΩ, RL = 10 kΩ, VTP = −1.5 V, kp = 2 mA/V², λ = 0.02 V⁻¹, signal amplitude = 10 mV peak, signal frequency = 1000 Hz, Rsig = 50 Ω. The analysis of that circuit, with frequency response switched on and the default capacitor values, gives:
| Operating region | Saturation |
|---|---|
| Drain Current (ID) | 1.615 mA |
| VSD | 8.771 V |
| gm | 2.541 mS |
| 1/gm | 393.5 Ω |
| ro | 30.97 kΩ |
| Voltage gain Av | 0.8008 V/V |
| Overall gain Gv (from Rsig) | 0.8007 V/V (−1.93 dB) |
| Input impedance Zin | 500 kΩ |
| Output impedance Zout | 325.3 Ω |
| Output amplitude at 1 kHz | 8.007 mV peak |
| Lower cut-off fL | 1.603 Hz |
| Upper cut-off fH | 235.7 MHz |
| Transistor power PT | 14.16 mW |
| Total supply power | 19.45 mW |
The transistor is in saturation with ID = 1.615 mA and VSD = 8.771 V, which leaves 2.691 V of undistorted output swing. The stage has a voltage gain of 0.8008 V/V, so a 10 mV peak input signal produces an output of about 8.007 mV peak, in phase with the input. The mid-band region extends from 1.603 Hz to 235.7 MHz. Change any value above to see how the results move.
Key characteristics of the common-drain stage
| Property | Typical behavior | Default example |
|---|---|---|
| Voltage gain | < 1, non-inverting | 0.8008 V/V |
| Current gain | Very high | 40.04 A/A |
| Power gain | ≈ current gain | 32.06 |
| Input impedance | Very high (bias resistors) | 500 kΩ |
| Output impedance | Low (≈ 1/gm ∥ RS) | 325.3 Ω |
| Phase shift | 0° | 0° |
| Typical uses | Buffers for high-impedance sources, level shifters | |
Design tips
- Increase ID to raise gm. That pushes the gain closer to one and lowers the output impedance.
- The DC output sits about VGS away from the gate. Account for this level shift when the next stage is DC-coupled.
- The body effect is not modeled here. In an integrated circuit where the body is tied to a supply rail, the real gain is somewhat lower.
Frequently asked questions
Why is the gain of a source follower less than one?
Part of the input voltage is needed to change VGS and so change the drain current. Only the rest appears at the output, giving Av = gm·RL′/(1 + gm·RL′).
What is a source follower used for?
Buffering. It accepts a signal at very high impedance and delivers it at low impedance, so a sensor or high-resistance stage can drive a heavier load without being loaded down.
How does a source follower compare with an emitter follower?
The source follower has a much higher input impedance because the gate draws no current, but a higher output impedance and a gain further from one, because MOSFET transconductance is lower than BJT transconductance at the same current.
How large should the gate divider resistors be?
As large as practical, usually hundreds of kilohms to a few megohms. They carry no gate current, so their value does not affect the bias voltage, only the input impedance and the noise. Very large values make the circuit sensitive to leakage and to pickup.
Why is VTP entered as a negative number?
By convention the threshold of a p-channel enhancement MOSFET is negative: the gate must be pulled below the source to turn it on. The calculator uses |VTP| internally and warns you if you enter a positive value.
What voltage gain does this CD amplifier give with the default values?
With the default components the calculator gives Av = 0.8008 V/V (−1.93 dB) from the gate to the load, and an overall gain of 0.8007 V/V from the 50 Ω signal source, with Zin = 500 kΩ and Zout = 325.3 Ω.