Fixed Bias PMOS Common Gate Calculator

About this calculator

This fixed bias PMOS common gate calculator analyzes a common-gate amplifier built with an enhancement-mode p-channel MOSFET and fixed gate bias. Enter your component values and it immediately finds the DC operating point (I_D, V_SD and the operating region), the small-signal parameters, voltage, current and power gain, input and output impedance, the output waveform with its clipping limits, the frequency response and the power dissipated in every component. Each result can be expanded to show the equation used and the numbers substituted into it, so you can follow or check the working by hand.

How to use it

1. Enter the supply rails (V_DD and V_SS; use 0 V for a grounded lower rail).
2. Type the resistor values and pick Ω, kΩ or MΩ, or type suffixes directly, such as 4.7k or 1M. Enter inf for an open-circuit load.
3. Set the MOSFET parameters: threshold voltage, device constant k, channel-length modulation λ and the square-law form your textbook uses.
4. Enter the signal amplitude, frequency and source resistance R_sig.
5. Switch on Frequency Response to add the coupling and internal capacitances and see the Bode plot, f_L and f_H.
6. Use the link button to copy a URL that reopens the calculator with your values.

How the common gate amplifier works

In the common-gate (CG) amplifier the gate is held at AC ground, directly or through a bypass capacitor. The signal is applied to the source and the output is taken from the drain. It is the MOSFET counterpart of the BJT common-base stage.

The signal source must supply the full drain current, so the input impedance is low, about 1/g_m in parallel with R_S. The current gain is close to one, and the voltage gain g_m·(R_D ∥ R_L) is non-inverting. Because the gate is grounded for AC, the gate–drain capacitance C_gd is not multiplied by the Miller effect, which gives the CG stage a wide bandwidth.

The common-gate stage is used as a current buffer, in RF low-noise amplifiers where its input resistance can be matched to 50 Ω, and as the upper device of the cascode. In this calculator the gate is biased either from V_GG through R_G or from an R₁–R₂ divider, with a capacitor C_g holding it at AC ground.

Fixed gate bias

In fixed gate bias the gate is connected to a bias voltage V_GG through a resistor R_G. Since no current flows into the gate, there is no voltage drop across R_G and V_G = V_GG exactly. R_G only sets the input impedance seen by the signal, so it is usually chosen in the megohm range.

With R_S = 0 the overdrive is fixed at V_OV = (V_DD − V_GG) − |V_TP|, and the drain current I_D = ½·k·V_OV² depends strongly on the threshold voltage, which varies between devices. Adding R_S creates self-stabilizing feedback: more current raises the source voltage and reduces the overdrive. The calculator then solves the resulting quadratic exactly, V_OV = [−1 + √(1 + 2k·R_S·(V_drive − |V_t|))]/(k·R_S).

PMOS polarity and the square-law model

An enhancement-mode PMOS transistor conducts when the gate is more negative than the source by at least |V_TP|; V_TP itself is entered as a negative number. Current flows from source to drain, so the source connects toward the positive supply. The calculator reports V_SG and V_SD to keep the numbers positive, and the device is in saturation when V_SD ≥ V_SG − |V_TP| = V_OV. Holes have roughly two to three times lower mobility than electrons, so a PMOS needs a wider channel to reach the same k_p as an NMOS. Once k is entered, the small-signal behavior is identical.

For the complementary circuit, see the Fixed Bias NMOS Common Gate calculator. Comparing the two is a quick way to check your PMOS/NMOS sign conventions.

Equations used

The calculator follows the standard two-step method taught in electronics courses. It first solves the DC bias circuit with all capacitors open, then replaces the transistor with its small-signal model and the capacitors with short circuits to find the mid-band AC behavior. These are the equations for this common-gate circuit with the default component values.

DC analysis

1. Gate Voltage (VG)VG = VGG − IG·RG = VGG (IG = 0)
2. Overdrive Voltage (VOV)VSG = (VDD − VG) − ID·RS, ID = ½k·VOV² ⇒ VOV = [−1 + √(1 + 2k·RS·(VDD − VG − |VTP|))] / (k·RS)
3. Drain Current (ID)ID = ½·k·VOV² (saturation assumed, λ neglected for bias)
4. VSDVSD = (VDD − VSS) − ID·(RD + RS)

Small-signal analysis

1. Transconductance (gm)gm = k·VOV = 2·ID / VOV
2. Output Resistance (ro)ro = 1 / (λ·ID)
3. AC Load (RL′)RL′ = RD ∥ RL
4. Voltage Gain (Av = vo / vs_in)Av = gm·RL′ (non-inverting)
5. Overall Gain (Gv = vo / vs)Gv = Av × Zin / (Zin + Rsig)
6. Current Gain (Ai = io / ii)Ai = Av × Zin / RL
7. Power Gain (Ap)Ap = |Av × Ai|
8. Input Impedance (Zin)Zin = RS ∥ (1/gm)
9. Output Impedance (Zout)Zout = RD ∥ ro·[1 + gm·(RS ∥ Rsig)]

The frequency-response section adds one low-frequency pole for each coupling or bypass capacitor, using the resistance that capacitor sees (short-circuit time constants), and estimates the upper cut-off frequency from the transistor’s internal capacitances using open-circuit time constants. The exact −3 dB points are then found numerically from the combined response.

Worked example

The calculator opens with a ready-to-use example circuit: V_DD = 5 V, V_SS = −12 V, V_GG = 0 V, R_G = 1 MΩ, R_D = 4.7 kΩ, R_S = 2 kΩ, R_L = 10 kΩ, V_TP = −1.5 V, k_p = 2 mA/V², λ = 0.02 V⁻¹, signal amplitude = 10 mV peak, signal frequency = 1000 Hz, R_sig = 50 Ω. The analysis of that circuit, with frequency response switched on and the default capacitor values, gives:

The transistor is in saturation with I_D = 1.202 mA and V_SD = 8.948 V, which leaves 3.843 V of undistorted output swing. The stage has a voltage gain of 7.01 V/V, so a 10 mV peak input signal produces an output of about 57.8 mV peak, in phase with the input. The mid-band region extends from 377.7 Hz to 94.35 MHz. Change any value above to see how the results move.

Key characteristics of the common-gate stage

Design tips

• Match Z_in = R_S ∥ 1/g_m to the source resistance when the stage terminates a cable or antenna.
• Because the input current flows through R_sig, a high source resistance loses most of the signal. The overall gain falls quickly as R_sig grows.
• Make the gate bypass capacitor C_g large enough that the gate really is at AC ground across the whole signal band. The analysis assumes it is.

Frequently asked questions