Voltage Divider NMOS Common Gate Calculator

Q: Is the common-gate amplifier inverting?

No. Raising the source voltage reduces VGS, which lowers the drain current and raises the drain voltage. The output is in phase with the input.

Q: Which form of the MOSFET current equation does the calculator use?

Both. By default it uses ID = ½·k·(VGS − Vt)², common in Sedra/Smith and Razavi. Switch “Square-law form” to ID = K·(VGS − Vt)² to enter the constant as used in Neamen, Boylestad and many datasheets.

Q: What voltage gain does this CG amplifier give with the default values?

With the default components the calculator gives Av = 5.748 V/V (15.2 dB) from the source to the load, and an overall gain of 4.93 V/V from the 50 Ω signal source, with Zin = 301.5 Ω and Zout = 3.056 kΩ.

About this calculator

This voltage divider bias NMOS common gate calculator analyzes a common-gate amplifier built with an enhancement-mode n-channel MOSFET and a voltage-divider bias network. Enter your component values and it immediately finds the DC operating point (I_D, V_DS and the operating region), the small-signal parameters, voltage, current and power gain, input and output impedance, the output waveform with its clipping limits, the frequency response and the power dissipated in every component. Each result can be expanded to show the equation used and the numbers substituted into it, so you can follow or check the working by hand.

How to use it

Enter the supply rails (V_DD and V_SS; use 0 V for a grounded lower rail).
Type the resistor values and pick Ω, kΩ or MΩ, or type suffixes directly, such as 4.7k or 1M. Enter inf for an open-circuit load.
Set the MOSFET parameters: threshold voltage, device constant k, channel-length modulation λ and the square-law form your textbook uses.
Enter the signal amplitude, frequency and source resistance R_sig.
Switch on Frequency Response to add the coupling and internal capacitances and see the Bode plot, f_L and f_H.
Use the link button to copy a URL that reopens the calculator with your values.

How the common gate amplifier works

In the common-gate (CG) amplifier the gate is held at AC ground, directly or through a bypass capacitor. The signal is applied to the source and the output is taken from the drain. It is the MOSFET counterpart of the BJT common-base stage.

The signal source must supply the full drain current, so the input impedance is low, about 1/g_m in parallel with R_S. The current gain is close to one, and the voltage gain g_m·(R_D ∥ R_L) is non-inverting. Because the gate is grounded for AC, the gate–drain capacitance C_gd is not multiplied by the Miller effect, which gives the CG stage a wide bandwidth.

The common-gate stage is used as a current buffer, in RF low-noise amplifiers where its input resistance can be matched to 50 Ω, and as the upper device of the cascode. In this calculator the gate is biased either from V_GG through R_G or from an R₁–R₂ divider, with a capacitor C_g holding it at AC ground.

Voltage-divider gate bias

A resistive divider sets the gate voltage: V_G = V_SS + (V_DD − V_SS)·R₂/(R₁ + R₂). Because the gate draws no current, this voltage is exact. Unlike the BJT divider, there is no base current to load it, and the resistors can be made very large (megohms) to keep the input impedance R₁ ∥ R₂ high.

The source resistor R_S provides negative feedback that stabilizes the drain current against threshold-voltage and k variations. With a source resistor the overdrive voltage satisfies V_OV = (V_G − V_SS) − I_D·R_S − V_TN together with I_D = ½·k·V_OV². The calculator solves this pair exactly and then checks whether the transistor is in saturation, triode or cutoff.

NMOS polarity and the square-law model

An enhancement-mode NMOS transistor conducts when the gate is more positive than the source by at least the threshold voltage V_TN, which is a positive number. Current flows from drain to source. The device is in saturation, the amplifying region, when V_DS ≥ V_GS − V_TN = V_OV, where I_D = ½·k_n·V_OV². Textbooks write the constant in two ways: k_n = µ_nC_ox·W/L with the ½ shown explicitly, or K = ½·k_n with I_D = K·V_OV². Choose the matching “Square-law form” so the results agree with your course or datasheet.

For the complementary circuit, see the Voltage Divider Bias PMOS Common Gate calculator. Comparing the two is a quick way to check your PMOS/NMOS sign conventions.

Equations used

The calculator follows the standard two-step method taught in electronics courses. It first solves the DC bias circuit with all capacitors open, then replaces the transistor with its small-signal model and the capacitors with short circuits to find the mid-band AC behavior. These are the equations for this common-gate circuit with the default component values.

DC analysis

Gate Voltage (VG)VG = VSS + (VDD − VSS) × R2 / (R1 + R2) (IG = 0)
Overdrive Voltage (VOV)VGS = (VG − VSS) − ID·RS, ID = ½k·VOV² ⇒ VOV = [−1 + √(1 + 2k·RS·(VG − VSS − VTN))] / (k·RS)
Drain Current (ID)ID = ½·k·VOV² (saturation assumed, λ neglected for bias)
VDSVDS = (VDD − VSS) − ID·(RD + RS)

Small-signal analysis

Transconductance (gm)gm = k·VOV = 2·ID / VOV
Output Resistance (ro)ro = 1 / (λ·ID)
AC Load (RL′)RL′ = RD ∥ RL
Voltage Gain (Av = vo / vs_in)Av = gm·RL′ (non-inverting)
Overall Gain (Gv = vo / vs)Gv = Av × Zin / (Zin + Rsig)
Current Gain (Ai = io / ii)Ai = Av × Zin / RL
Power Gain (Ap)Ap = |Av × Ai|
Input Impedance (Zin)Zin = RS ∥ (1/gm)
Output Impedance (Zout)Zout = RD ∥ ro·[1 + gm·(RS ∥ Rsig)]

The frequency-response section adds one low-frequency pole for each coupling or bypass capacitor, using the resistance that capacitor sees (short-circuit time constants), and estimates the upper cut-off frequency from the transistor’s internal capacitances using open-circuit time constants. The exact −3 dB points are then found numerically from the combined response.

Worked example

The calculator opens with a ready-to-use example circuit: V_DD = 12 V, V_SS = 0 V, R₁ = 2 MΩ, R₂ = 1 MΩ, R_D = 3.3 kΩ, R_S = 1 kΩ, R_L = 10 kΩ, V_TN = 1.5 V, k_n = 2 mA/V², λ = 0.02 V⁻¹, signal amplitude = 10 mV peak, signal frequency = 1000 Hz, R_sig = 50 Ω. The analysis of that circuit, with frequency response switched on and the default capacitor values, gives:

Operating region	Saturation
Drain Current (I_D)	1.342 mA
V_DS	6.231 V
g_m	2.317 mS
1/g_m	431.7 Ω
r_o	37.27 kΩ
Voltage gain A_v	5.748 V/V
Overall gain G_v (from R_sig)	4.93 V/V (13.9 dB)
Input impedance Z_in	301.5 Ω
Output impedance Z_out	3.056 kΩ
Output amplitude at 1 kHz	44.91 mV peak
Lower cut-off f_L	452.8 Hz
Upper cut-off f_H	120 MHz
Transistor power P_T	8.36 mW
Total supply power	16.15 mW

The transistor is in saturation with I_D = 1.342 mA and V_DS = 6.231 V, which leaves 3.329 V of undistorted output swing. The stage has a voltage gain of 5.748 V/V, so a 10 mV peak input signal produces an output of about 44.91 mV peak, in phase with the input. The mid-band region extends from 452.8 Hz to 120 MHz. Change any value above to see how the results move.

Key characteristics of the common-gate stage

Property	Typical behavior	Default example
Voltage gain	Moderate to high, non-inverting	5.748 V/V
Current gain	≈ 1	0.1733 A/A
Power gain	Moderate	0.9962
Input impedance	Low (≈ 1/g_m ∥ R_S)	301.5 Ω
Output impedance	High (≈ R_D)	3.056 kΩ
Phase shift	0°	0°
Typical uses	RF low-noise amplifiers, current buffers, cascodes

Design tips

Match Z_in = R_S ∥ 1/g_m to the source resistance when the stage terminates a cable or antenna.
Because the input current flows through R_sig, a high source resistance loses most of the signal. The overall gain falls quickly as R_sig grows.
Make the gate bypass capacitor C_g large enough that the gate really is at AC ground across the whole signal band. The analysis assumes it is.

Frequently asked questions

Why is the input impedance of a common-gate amplifier low?

The signal drives the source terminal, and the source carries the full channel current. A small change in source voltage changes V_GS and therefore the drain current by g_m·v_s, so the input looks like a resistance of 1/g_m.

Is the common-gate amplifier inverting?

No. Raising the source voltage reduces V_GS, which lowers the drain current and raises the drain voltage. The output is in phase with the input.

When should I use a common-gate stage instead of common-source?

When you need a low, well-defined input resistance (for example to terminate a 50 Ω line), a wide bandwidth without the Miller effect, or a current buffer such as the upper device in a cascode.

How large should the gate divider resistors be?

As large as practical, usually hundreds of kilohms to a few megohms. They carry no gate current, so their value does not affect the bias voltage, only the input impedance and the noise. Very large values make the circuit sensitive to leakage and to pickup.

Which form of the MOSFET current equation does the calculator use?

Both. By default it uses I_D = ½·k·(V_GS − V_t)², common in Sedra/Smith and Razavi. Switch “Square-law form” to I_D = K·(V_GS − V_t)² to enter the constant as used in Neamen, Boylestad and many datasheets.

What voltage gain does this CG amplifier give with the default values?

With the default components the calculator gives A_v = 5.748 V/V (15.2 dB) from the source to the load, and an overall gain of 4.93 V/V from the 50 Ω signal source, with Z_in = 301.5 Ω and Z_out = 3.056 kΩ.

Voltage Divider Bias NMOS Common Gate Calculator

Circuit Schematic

DC Operating Point

Gain Analysis

Impedance

AC Signal Analysis

Power Dissipation

Model & Assumptions