About this calculator
This fixed bias PNP BJT common emitter calculator analyzes a common-emitter amplifier built with a PNP bipolar junction transistor and fixed base-resistor bias. Enter your component values and it immediately finds the DC operating point (IC, VEC and the operating region), the small-signal parameters, voltage, current and power gain, input and output impedance, the output waveform with its clipping limits, the frequency response and the power dissipated in every component. Each result can be expanded to show the equation used and the numbers substituted into it, so you can follow or check the working by hand.
How to use it
- Enter the supply rails (VCC and VEE; use 0 V for a grounded lower rail).
- Type the resistor values and pick Ω, kΩ or MΩ, or type suffixes directly, such as
4.7kor1M. Enterinffor an open-circuit load. - Set the transistor parameters β, VBE(on), VCE(sat), temperature and Early voltage.
- Enter the signal amplitude, frequency and source resistance Rsig.
- Switch on Frequency Response to add the coupling, bypass and internal capacitances and see the Bode plot, fL and fH.
- Use the link button to copy a URL that reopens the calculator with your values.
How the common emitter amplifier works
In the common-emitter (CE) amplifier the input signal is applied to the base, the output is taken from the collector, and the emitter is the terminal shared by input and output. The emitter sits at AC ground, either directly or through a bypass capacitor. A small change in base–emitter voltage produces a large change in collector current through the transconductance gm = IC/VT, and that current flows through the collector resistor to create the output voltage.
Because a rising base voltage increases the collector current and pulls the collector voltage down, the output is inverted: there is a 180° phase shift between input and output. The CE stage delivers both voltage gain and current gain, so its power gain is the highest of the three BJT configurations. Its input impedance is moderate, roughly rπ in parallel with the bias resistors, and its output impedance is approximately RC. That is why connecting a load resistor through Cc2 noticeably reduces the gain.
An unbypassed emitter resistor RE adds local negative feedback, known as emitter degeneration. It lowers the gain to roughly −RC′/RE, but makes the gain far less dependent on β and temperature, raises the input resistance by about (β + 1)·RE and reduces distortion. A bypass capacitor Ce restores the full gain at signal frequencies while keeping RE in place for DC stability. The calculator lets you switch between the bypassed and unbypassed cases with one toggle.
Fixed (base-resistor) bias
Fixed bias sets the base current with a single resistor RB from a bias source VBB. In many textbook circuits that source is simply the supply VCC, so enter the same value in both fields to model that case. Including the emitter resistor, the base loop gives IB = (VCC − VEB − VBB)/(RB + (β + 1)·RE), and then IC = β·IB.
Without RE the collector current is directly proportional to β. Because β varies by a factor of two or more between transistors of the same type, and also changes with temperature, a plain fixed-bias design can move far from its intended Q-point when the transistor is replaced. An emitter resistor helps: when (β + 1)·RE is large compared with RB, the current is set mostly by RE instead of β.
PNP polarity and conventions
A PNP transistor is the mirror image of an NPN: it conducts when the base is about 0.6–0.7 V below the emitter, and current flows into the emitter and out of the base and collector. The emitter therefore connects toward the positive supply and the collector toward the negative rail or ground. To keep the numbers positive, the calculator reports VEB, VEC and VBC for PNP stages, and every bias equation is the NPN equation with all polarities reversed. The small-signal model (gm, rπ, ro) is identical, so a PNP stage biased at the same current has the same gain and impedances as its NPN counterpart.
For the complementary circuit, see the Fixed Bias NPN BJT Common Emitter calculator. Comparing the two is a quick way to check your PNP/NPN sign conventions.
Equations used
The calculator follows the standard two-step method taught in electronics courses. It first solves the DC bias circuit with all capacitors open, then replaces the transistor with its small-signal model and the capacitors with short circuits to find the mid-band AC behavior. These are the equations for this common-emitter circuit with the default component values.
DC analysis
- Base Current (IB)
IB = (VCC − VEB − VBB) / (RB + (β + 1)·RE) - Collector Current (IC)
IC = β × IB - Emitter Current (IE)
IE = (β + 1) × IB - VEC (assuming active)
VEC = (VCC − VEE) − IC·RC − IE·RE
Small-signal analysis
- Thermal Voltage (VT)
VT = k·T / q = T / 11604.5 - Transconductance (gm)
gm = IC / VT - Base–Emitter Resistance (rπ)
rπ = β / gm - Output Resistance (ro)
ro = VA / IC - AC Load (RL′)
RL′ = RC ∥ RL ∥ ro - Voltage Gain (Av = vo / vb)
Av = −gm·RL′ (RE bypassed) - Overall Gain (Gv = vo / vs)
Gv = Av × Zin / (Zin + Rsig) - Current Gain (Ai = io / ii)
Ai = Av × Zin / RL - Power Gain (Ap)
Ap = |Av × Ai| - Input Impedance (Zin)
Zin = RB ∥ rπ - Output Impedance (Zout)
Zout = RC ∥ ro
The frequency-response section adds one low-frequency pole for each coupling or bypass capacitor, using the resistance that capacitor sees (short-circuit time constants), and estimates the upper cut-off frequency from the transistor’s internal capacitances using open-circuit time constants. The exact −3 dB points are then found numerically from the combined response.
Worked example
The calculator opens with a ready-to-use example circuit: VCC = 12 V, VEE = 0 V, VBB = 7 V, RB = 100 kΩ, RC = 2.2 kΩ, RE = 1 kΩ, RL = 10 kΩ, β = 100, VEB(on) = 0.7 V, VEC(sat) = 0.2 V, T = 300 K, VA = 100 V, signal amplitude = 10 mV peak, signal frequency = 1000 Hz, Rsig = 50 Ω. The analysis of that circuit, with frequency response switched on and the default capacitor values, gives:
| Operating region | Forward-active |
|---|---|
| Collector Current (IC) | 2.139 mA |
| VEC | 5.133 V |
| gm | 82.75 mS |
| rπ | 1.208 kΩ |
| ro | 46.74 kΩ |
| Voltage gain Av | −143.7 V/V |
| Overall gain Gv (from Rsig) | −137.9 V/V (42.8 dB) |
| Input impedance Zin | 1.194 kΩ |
| Output impedance Zout | 2.101 kΩ |
| Output amplitude at 1 kHz | 1.368 V peak |
| Lower cut-off fL | 130.6 Hz |
| Upper cut-off fH | 8.922 MHz |
| Transistor power PT | 11 mW |
| Total supply power | 25.78 mW |
The transistor is in the forward-active region with IC = 2.139 mA and VEC = 5.133 V, which leaves 3.858 V of undistorted output swing. The stage has a voltage gain of −143.7 V/V, so a 10 mV peak input signal produces an output of about 1.368 V peak, inverted with respect to the input. The mid-band region extends from 130.6 Hz to 8.922 MHz. Change any value above to see how the results move.
Key characteristics of the common-emitter stage
| Property | Typical behavior | Default example |
|---|---|---|
| Voltage gain | High, inverting | −143.7 V/V |
| Current gain | High | −17.16 A/A |
| Power gain | Highest of the three | 2465 |
| Input impedance | Medium (≈ rπ ∥ bias resistors) | 1.194 kΩ |
| Output impedance | High (≈ RC) | 2.101 kΩ |
| Phase shift | 180° | 180° |
| Typical uses | General voltage amplification, audio pre-amplifiers, driver stages | |
Design tips
- Place the Q-point near the middle of the load line so the output can swing equally in both directions. The load-line chart and the “maximum undistorted swing” result show how much headroom you have.
- Keep the base–emitter signal below about 10 mV peak in a bypassed stage. Larger signals make the exponential diode law visibly distort the output.
- If the gain must be predictable, leave part of RE unbypassed. The gain then approaches −RC′/RE regardless of β.
- The bypass capacitor usually sets the lower cut-off frequency because it sees a very small resistance, about re + Rs′/(β + 1). It therefore needs the largest value of the three capacitors.
Frequently asked questions
Why does a common-emitter amplifier invert the signal?
When the base voltage rises, the collector current increases. The larger current produces a larger voltage drop across the collector resistor, so the collector voltage falls. The output therefore moves opposite to the input, which is a 180° phase shift.
What limits the high-frequency response of a CE amplifier?
Mostly the Miller effect. The base–collector capacitance Cµ connects the input to an inverted, amplified output, so the input source sees it multiplied by roughly (1 + gm·RL′). Together with Cπ this forms the dominant high-frequency pole. The calculator estimates fH with the open-circuit time-constant method.
How does the load resistor change the gain?
For AC signals the load RL appears in parallel with RC and ro, so the effective collector load RL′ = RC ∥ RL ∥ ro becomes smaller and the gain −gm·RL′ drops. Enter inf for RL to see the unloaded gain.
Why is fixed bias considered unstable?
Its collector current is roughly β times a base current that the circuit sets independently of the transistor. Any change in β, from part-to-part spread or temperature, moves the collector current and the Q-point by the same proportion, and can push the transistor into saturation.
Why would I use a PNP transistor instead of an NPN?
PNP stages let a circuit work “upside down”: the emitter ties to the positive rail, which is convenient for high-side switching, current sources that push current into a load, level shifting between stages, and complementary push-pull output stages. Silicon PNP devices have somewhat lower β and speed than matched NPN parts, but the analysis is the same.
What voltage gain does this CE amplifier give with the default values?
With the default components the calculator gives Av = −143.7 V/V (43.1 dB) from the base to the load, and an overall gain of −137.9 V/V from the 50 Ω signal source, with Zin = 1.194 kΩ and Zout = 2.101 kΩ.