Voltage Divider Bias PNP BJT Common Emitter Calculator

About this calculator

This voltage divider bias PNP BJT common emitter calculator analyzes a common-emitter amplifier built with a PNP bipolar junction transistor and a voltage-divider bias network. Enter your component values and it immediately finds the DC operating point (I_C, V_EC and the operating region), the small-signal parameters, voltage, current and power gain, input and output impedance, the output waveform with its clipping limits, the frequency response and the power dissipated in every component. Each result can be expanded to show the equation used and the numbers substituted into it, so you can follow or check the working by hand.

How to use it

1. Enter the supply rails (V_CC and V_EE; use 0 V for a grounded lower rail).
2. Type the resistor values and pick Ω, kΩ or MΩ, or type suffixes directly, such as 4.7k or 1M. Enter inf for an open-circuit load.
3. Set the transistor parameters β, V_BE(on), V_CE(sat), temperature and Early voltage.
4. Enter the signal amplitude, frequency and source resistance R_sig.
5. Switch on Frequency Response to add the coupling, bypass and internal capacitances and see the Bode plot, f_L and f_H.
6. Use the link button to copy a URL that reopens the calculator with your values.

How the common emitter amplifier works

In the common-emitter (CE) amplifier the input signal is applied to the base, the output is taken from the collector, and the emitter is the terminal shared by input and output. The emitter sits at AC ground, either directly or through a bypass capacitor. A small change in base–emitter voltage produces a large change in collector current through the transconductance g_m = I_C/V_T, and that current flows through the collector resistor to create the output voltage.

Because a rising base voltage increases the collector current and pulls the collector voltage down, the output is inverted: there is a 180° phase shift between input and output. The CE stage delivers both voltage gain and current gain, so its power gain is the highest of the three BJT configurations. Its input impedance is moderate, roughly r_π in parallel with the bias resistors, and its output impedance is approximately R_C. That is why connecting a load resistor through C_c2 noticeably reduces the gain.

An unbypassed emitter resistor R_E adds local negative feedback, known as emitter degeneration. It lowers the gain to roughly −R_C′/R_E, but makes the gain far less dependent on β and temperature, raises the input resistance by about (β + 1)·R_E and reduces distortion. A bypass capacitor C_e restores the full gain at signal frequencies while keeping R_E in place for DC stability. The calculator lets you switch between the bypassed and unbypassed cases with one toggle.

Voltage-divider bias

Voltage-divider bias, also called four-resistor bias, is the most widely used discrete BJT bias network. R₁ and R₂ form a divider that holds the base near a fixed voltage, and R_E converts that voltage into an emitter current. Replacing the divider by its Thevenin equivalent gives V_TH = V_EE + (V_CC − V_EE)·R₂/(R₁ + R₂) and R_TH = R₁ ∥ R₂, and then I_B = (V_CC − V_EB − V_TH)/(R_TH + (β + 1)·R_E).

When (β + 1)·R_E is much larger than R_TH (a common rule of thumb is a factor of ten), the emitter current hardly depends on β at all. The calculator always uses the exact Thevenin equation instead of the stiff-divider approximation, so it stays accurate even for a “soft” divider with large resistors. Remember that the divider also appears in parallel with the transistor’s input, so very small R₁ and R₂ stabilize the bias at the cost of input impedance.

PNP polarity and conventions

A PNP transistor is the mirror image of an NPN: it conducts when the base is about 0.6–0.7 V below the emitter, and current flows into the emitter and out of the base and collector. The emitter therefore connects toward the positive supply and the collector toward the negative rail or ground. To keep the numbers positive, the calculator reports V_EB, V_EC and V_BC for PNP stages, and every bias equation is the NPN equation with all polarities reversed. The small-signal model (g_m, r_π, r_o) is identical, so a PNP stage biased at the same current has the same gain and impedances as its NPN counterpart.

For the complementary circuit, see the Voltage Divider Bias NPN BJT Common Emitter calculator. Comparing the two is a quick way to check your PNP/NPN sign conventions.

Equations used

The calculator follows the standard two-step method taught in electronics courses. It first solves the DC bias circuit with all capacitors open, then replaces the transistor with its small-signal model and the capacitors with short circuits to find the mid-band AC behavior. These are the equations for this common-emitter circuit with the default component values.

DC analysis

1. Thevenin Base Voltage (VTH)VTH = VEE + (VCC − VEE) × R2 / (R1 + R2)
2. Thevenin Base Resistance (RTH)RTH = R1 ∥ R2
3. Base Current (IB)IB = (VCC − VEB − VTH) / (RTH + (β + 1)·RE)
4. Collector Current (IC)IC = β × IB
5. Emitter Current (IE)IE = (β + 1) × IB
6. VEC (assuming active)VEC = (VCC − VEE) − IC·RC − IE·RE

Small-signal analysis

1. Thermal Voltage (VT)VT = k·T / q = T / 11604.5
2. Transconductance (gm)gm = IC / VT
3. Base–Emitter Resistance (rπ)rπ = β / gm
4. Output Resistance (ro)ro = VA / IC
5. AC Load (RL′)RL′ = RC ∥ RL ∥ ro
6. Voltage Gain (Av = vo / vb)Av = −gm·RL′ (RE bypassed)
7. Overall Gain (Gv = vo / vs)Gv = Av × Zin / (Zin + Rsig)
8. Current Gain (Ai = io / ii)Ai = Av × Zin / RL
9. Power Gain (Ap)Ap = |Av × Ai|
10. Input Impedance (Zin)Zin = RTH ∥ rπ
11. Output Impedance (Zout)Zout = RC ∥ ro

The frequency-response section adds one low-frequency pole for each coupling or bypass capacitor, using the resistance that capacitor sees (short-circuit time constants), and estimates the upper cut-off frequency from the transistor’s internal capacitances using open-circuit time constants. The exact −3 dB points are then found numerically from the combined response.

Worked example

The calculator opens with a ready-to-use example circuit: V_CC = 12 V, V_EE = 0 V, R₁ = 10 kΩ, R₂ = 47 kΩ, R_C = 3.3 kΩ, R_E = 1 kΩ, R_L = 10 kΩ, β = 100, V_EB(on) = 0.7 V, V_EC(sat) = 0.2 V, T = 300 K, VA = 100 V, signal amplitude = 10 mV peak, signal frequency = 1000 Hz, R_sig = 50 Ω. The analysis of that circuit, with frequency response switched on and the default capacitor values, gives:

The transistor is in the forward-active region with I_C = 1.286 mA and V_EC = 6.456 V, which leaves 3.192 V of undistorted output swing. The stage has a voltage gain of −119.6 V/V, so a 10 mV peak input signal produces an output of about 1.157 V peak, inverted with respect to the input. The mid-band region extends from 80.79 Hz to 9.364 MHz. Change any value above to see how the results move.

Key characteristics of the common-emitter stage

Design tips

• Place the Q-point near the middle of the load line so the output can swing equally in both directions. The load-line chart and the “maximum undistorted swing” result show how much headroom you have.
• Keep the base–emitter signal below about 10 mV peak in a bypassed stage. Larger signals make the exponential diode law visibly distort the output.
• If the gain must be predictable, leave part of R_E unbypassed. The gain then approaches −R_C′/R_E regardless of β.
• The bypass capacitor usually sets the lower cut-off frequency because it sees a very small resistance, about r_e + R_s′/(β + 1). It therefore needs the largest value of the three capacitors.

Frequently asked questions