Voltage Divider NMOS Common Source Calculator

Q: Why does a MOSFET common-source stage have less gain than a BJT common-emitter stage?

A BJT’s transconductance is IC/VT with VT ≈ 26 mV, while a MOSFET’s is 2·ID/VOV with VOV usually a few hundred millivolts or more. At equal current the BJT has several times more gm, and therefore more gain with the same load.

Q: What happens if the MOSFET enters the triode region?

In triode the drain current depends strongly on VDS, so the device behaves like a voltage-controlled resistor instead of a current source. The gain collapses and the output waveform is clipped. The calculator detects triode operation and solves the circuit with the triode equation.

Q: Which form of the MOSFET current equation does the calculator use?

Both. By default it uses ID = ½·k·(VGS − Vt)², common in Sedra/Smith and Razavi. Switch “Square-law form” to ID = K·(VGS − Vt)² to enter the constant as used in Neamen, Boylestad and many datasheets.

Q: What voltage gain does this CS amplifier give with the default values?

With the default components the calculator gives Av = −5.43 V/V (14.7 dB) from the gate to the load, and an overall gain of −5.43 V/V from the 50 Ω signal source, with Zin = 767.4 kΩ and Zout = 4.373 kΩ.

About this calculator

This voltage divider bias NMOS common source calculator analyzes a common-source amplifier built with an enhancement-mode n-channel MOSFET and a voltage-divider bias network. Enter your component values and it immediately finds the DC operating point (I_D, V_DS and the operating region), the small-signal parameters, voltage, current and power gain, input and output impedance, the output waveform with its clipping limits, the frequency response and the power dissipated in every component. Each result can be expanded to show the equation used and the numbers substituted into it, so you can follow or check the working by hand.

How to use it

Enter the supply rails (V_DD and V_SS; use 0 V for a grounded lower rail).
Type the resistor values and pick Ω, kΩ or MΩ, or type suffixes directly, such as 4.7k or 1M. Enter inf for an open-circuit load.
Set the MOSFET parameters: threshold voltage, device constant k, channel-length modulation λ and the square-law form your textbook uses.
Enter the signal amplitude, frequency and source resistance R_sig.
Switch on Frequency Response to add the coupling, bypass and internal capacitances and see the Bode plot, f_L and f_H.
Use the link button to copy a URL that reopens the calculator with your values.

How the common source amplifier works

In the common-source (CS) amplifier the signal is applied to the gate, the output is taken from the drain, and the source is common to input and output. The source is either grounded directly or connected through a bypassed source resistor. A change in gate voltage produces a drain-current change g_m·v_gs, and that current develops the output voltage across R_D ∥ R_L. Like the BJT common-emitter stage, it is an inverting amplifier with a 180° phase shift.

The gate draws no DC current, so the input impedance is set only by the bias resistors (R_G, or R₁ ∥ R₂), typically in the megohm range. MOSFET transconductance is lower than that of a BJT at the same current, because g_m = 2·I_D/V_OV instead of I_C/V_T. A CS stage with resistor loads therefore usually has more modest voltage gain, often in the single or low double digits.

An unbypassed source resistor R_S adds negative feedback. It reduces the gain to −g_m·R_L′/(1 + g_m·R_S) but stabilizes it against device variation, and a bypass capacitor C_s removes that feedback at signal frequencies. The transistor must stay in saturation for amplification. If the drain swings too low, the device enters the triode region and the output clips.

Voltage-divider gate bias

A resistive divider sets the gate voltage: V_G = V_SS + (V_DD − V_SS)·R₂/(R₁ + R₂). Because the gate draws no current, this voltage is exact. Unlike the BJT divider, there is no base current to load it, and the resistors can be made very large (megohms) to keep the input impedance R₁ ∥ R₂ high.

The source resistor R_S provides negative feedback that stabilizes the drain current against threshold-voltage and k variations. With a source resistor the overdrive voltage satisfies V_OV = (V_G − V_SS) − I_D·R_S − V_TN together with I_D = ½·k·V_OV². The calculator solves this pair exactly and then checks whether the transistor is in saturation, triode or cutoff.

NMOS polarity and the square-law model

An enhancement-mode NMOS transistor conducts when the gate is more positive than the source by at least the threshold voltage V_TN, which is a positive number. Current flows from drain to source. The device is in saturation, the amplifying region, when V_DS ≥ V_GS − V_TN = V_OV, where I_D = ½·k_n·V_OV². Textbooks write the constant in two ways: k_n = µ_nC_ox·W/L with the ½ shown explicitly, or K = ½·k_n with I_D = K·V_OV². Choose the matching “Square-law form” so the results agree with your course or datasheet.

For the complementary circuit, see the Voltage Divider Bias PMOS Common Source calculator. Comparing the two is a quick way to check your PMOS/NMOS sign conventions.

Equations used

The calculator follows the standard two-step method taught in electronics courses. It first solves the DC bias circuit with all capacitors open, then replaces the transistor with its small-signal model and the capacitors with short circuits to find the mid-band AC behavior. These are the equations for this common-source circuit with the default component values.

DC analysis

Gate Voltage (VG)VG = VSS + (VDD − VSS) × R2 / (R1 + R2) (IG = 0)
Overdrive Voltage (VOV)VGS = (VG − VSS) − ID·RS, ID = ½k·VOV² ⇒ VOV = [−1 + √(1 + 2k·RS·(VG − VSS − VTN))] / (k·RS)
Drain Current (ID)ID = ½·k·VOV² (saturation assumed, λ neglected for bias)
VDSVDS = (VDD − VSS) − ID·(RD + RS)

Small-signal analysis

Transconductance (gm)gm = k·VOV = 2·ID / VOV
Output Resistance (ro)ro = 1 / (λ·ID)
AC Load (RL′)RL′ = RD ∥ RL ∥ ro
Voltage Gain (Av = vo / vg)Av = −gm·RL′
Overall Gain (Gv = vo / vs)Gv = Av × Zin / (Zin + Rsig)
Current Gain (Ai = io / ii)Ai = Av × Zin / RL
Power Gain (Ap)Ap = |Av × Ai|
Input Impedance (Zin)Zin = R1 ∥ R2 (gate draws no current)
Output Impedance (Zout)Zout = RD ∥ ro

The frequency-response section adds one low-frequency pole for each coupling or bypass capacitor, using the resistance that capacitor sees (short-circuit time constants), and estimates the upper cut-off frequency from the transistor’s internal capacitances using open-circuit time constants. The exact −3 dB points are then found numerically from the combined response.

Worked example

The calculator opens with a ready-to-use example circuit: V_DD = 12 V, V_SS = 0 V, R₁ = 3.3 MΩ, R₂ = 1 MΩ, R_D = 4.7 kΩ, R_S = 500 Ω, R_L = 10 kΩ, V_TN = 1.5 V, k_n = 2 mA/V², λ = 0.02 V⁻¹, signal amplitude = 10 mV peak, signal frequency = 1000 Hz, R_sig = 50 Ω. The analysis of that circuit, with frequency response switched on and the default capacitor values, gives:

Operating region	Saturation
Drain Current (I_D)	796.5 µA
V_DS	7.858 V
g_m	1.785 mS
1/g_m	560.3 Ω
r_o	62.78 kΩ
Voltage gain A_v	−5.43 V/V
Overall gain G_v (from R_sig)	−5.43 V/V (14.7 dB)
Input impedance Z_in	767.4 kΩ
Output impedance Z_out	4.373 kΩ
Output amplitude at 1 kHz	54.29 mV peak
Lower cut-off f_L	12.91 Hz
Upper cut-off f_H	89.32 MHz
Transistor power P_T	6.259 mW
Total supply power	9.591 mW

The transistor is in saturation with I_D = 796.5 µA and V_DS = 7.858 V, which leaves 2.547 V of undistorted output swing. The stage has a voltage gain of −5.43 V/V, so a 10 mV peak input signal produces an output of about 54.29 mV peak, inverted with respect to the input. The mid-band region extends from 12.91 Hz to 89.32 MHz. Change any value above to see how the results move.

Key characteristics of the common-source stage

Property	Typical behavior	Default example
Voltage gain	Moderate to high, inverting	−5.43 V/V
Current gain	Very high (gate draws no current)	−416.7 A/A
Power gain	High	2263
Input impedance	Very high (bias resistors)	767.4 kΩ
Output impedance	High (≈ R_D)	4.373 kΩ
Phase shift	180°	180°
Typical uses	General voltage amplification, sensor front ends

Design tips

Choose the overdrive voltage V_OV = V_GS − V_t deliberately. A small V_OV gives more transconductance per milliamp but less signal headroom. Keep the gate–source signal below about 0.2·V_OV.
Keep the drain–source voltage comfortably above V_OV plus the expected negative output peak so the transistor stays in saturation.
A source resistor makes I_D less sensitive to the threshold voltage, which can vary by several hundred millivolts between parts of the same type.
Because Z_in is so high, the input coupling capacitor can be small. Its pole is 1/(2π·C_c1·(R_sig + Z_in)).

Frequently asked questions

Why is the input impedance of a MOSFET amplifier so high?

The gate is insulated from the channel by a thin oxide layer, so essentially no DC current flows into it. The only path for the signal source is the bias network, which is why input impedances of several megohms are normal.

Why does a MOSFET common-source stage have less gain than a BJT common-emitter stage?

A BJT’s transconductance is I_C/V_T with V_T ≈ 26 mV, while a MOSFET’s is 2·I_D/V_OV with V_OV usually a few hundred millivolts or more. At equal current the BJT has several times more g_m, and therefore more gain with the same load.

What happens if the MOSFET enters the triode region?

In triode the drain current depends strongly on V_DS, so the device behaves like a voltage-controlled resistor instead of a current source. The gain collapses and the output waveform is clipped. The calculator detects triode operation and solves the circuit with the triode equation.

How large should the gate divider resistors be?

As large as practical, usually hundreds of kilohms to a few megohms. They carry no gate current, so their value does not affect the bias voltage, only the input impedance and the noise. Very large values make the circuit sensitive to leakage and to pickup.

Which form of the MOSFET current equation does the calculator use?

Both. By default it uses I_D = ½·k·(V_GS − V_t)², common in Sedra/Smith and Razavi. Switch “Square-law form” to I_D = K·(V_GS − V_t)² to enter the constant as used in Neamen, Boylestad and many datasheets.

What voltage gain does this CS amplifier give with the default values?

With the default components the calculator gives A_v = −5.43 V/V (14.7 dB) from the gate to the load, and an overall gain of −5.43 V/V from the 50 Ω signal source, with Z_in = 767.4 kΩ and Z_out = 4.373 kΩ.

Voltage Divider Bias NMOS Common Source Calculator

Circuit Schematic

DC Operating Point

Gain Analysis

Impedance

AC Signal Analysis

Power Dissipation

Model & Assumptions